Finally comes the declaration of the duty_cycle vector—this time, I used the alias keyword instead of creating a new signal. F or f. Some of the new features in VHDL-2008 are intended for verification only, not for design.

I'm not sure about other simulators.-Kurt I used alog -work mylibrary -pli myfile.sv

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Declare a signal in a package - a "global" signal. VHDL aggregates allow a value to be made up from a collection individual array or record elements. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests. If you need to use the same external name many times, it pays to use an alias: alias mysig is << signal .path.to.signal : subtype >>; QuestaSim version 6.5b supports VHDL 2008 external names. VHDL-2008 relaxes this and allows a flip-flop to be modelled like this: It is also permitted to use the selected signal assignment in a process: VHDL-2008 makes the generate statement much more flexible. [CDATA[// >